http://www.cs.washington.edu/education/courses/567/misc/document.html

CSE 567: Principles of Digital Systems Design

Carl Ebeling, Fall 1996


Notes on synthesis for homework #3.

Cadence online documentation.

To get to the Cadence online documenation, run "openbook". You'll probably have to source the $UW_VLSI_TOOLS/setups/cadence.cshrc file first. We use Verilog-XL simulator for all our simulation. The documentation you might want to look at are under "HDL Tools->Verilog-XL Simulation":

Synopsys online documentation.

To get to the Synopsys online documentation, run "iview". You'll probably have to source the $UW_VLSI_TOOLS/setups/synopsys.cshrc file first. The Synopsys documentation of interest includes:


ebeling@cs.washington.edu